Sr. Embedded Hardware Engineer

Experience Requirement: 3-7 years

About the

The role requires strong expertise in mixed-signal electronics, high-speed digital interfaces, RF circuit integration, FPGA based hardware, and power-supply design. The selected candidate is not required to perform detailed PCB layout; however, they must be capable of defining, reviewing, and approving PCB layout constraints for complex mixed-signal boards containing high-speed SERDES, PCIe, JESD204B/C, RF circuits, and sensitive analog signal chains.

• Develop system architectures, block diagrams, detailed schematics, component specifications, interface definitions, and design documentation.
• Design mixed-signal hardware incorporating high-speed ADCs, DACs, FPGAs, processors, memory devices, RF circuits, and power management components.
• Design and integrate JESD204B/C interfaces between high-speed data converters and FPGAs, including clocking, synchronization, SYSREF distribution, lane configuration, deterministic latency, and link validation.
• Design and integrate high-speed interfaces such as SERDES operating above 10 Gbps, PCIe, DDR3/DDR4, LVDS, Ethernet, and USB.
• Define and review signal-integrity, power-integrity, stack-up, routing, placement, grounding, shielding, return path, impedance-control, and length matching requirements.
• Work closely with PCB layout engineers to ensure that high-speed digital, sensitive analog, RF, and power circuits are implemented according to the required electrical and manufacturing constraints.
• Review PCB layouts for complex mixed-signal boards with more than 12 layers.
• Define layout constraints for high-speed differential pairs, SERDES channels, PCIe interfaces, JESD204B/C lanes, DDR interfaces, clock networks, RF traces, and sensitive analog signals.
• Perform or review channel-loss, impedance, crosstalk, return loss, eye diagram, timing, and power distribution network analyses.
• Design and review RF signal paths, including impedance matching, transmission line structures, RF component selection, filtering, grounding, shielding, and isolation from digital and power switching circuits.
• Design onboard power architectures incorporating buck converters, point of load regulators, low dropout regulators, sequencing circuits, monitoring circuits, and low noise power rails for analog, RF, digital, FPGA, ADC, and DAC devices.
• Conduct simulations and engineering analyses to verify electrical performance, signal integrity, power integrity, thermal performance, and design reliability.
• Collaborate with FPGA, embedded software, mechanical, RF, systems, and test engineers to ensure seamless hardware and software integration.
• Perform board bring up, hardware debugging, troubleshooting, performance characterization, and design optimization.
• Develop and execute test plans to validate functional performance, high-speed interface operation, RF performance, power integrity, environmental robustness, and compliance with applicable space standards.
• Support EMI/EMC, thermal, vibration, qualification, and environmental testing.
• Participate in schematic reviews, PCB layout reviews, design reviews, failure investigations, and continuous improvement initiatives.
• Prepare and maintain design specifications, interface-control documents, design-analysis reports, test procedures, test results, and technical reports.

Minimum

• At least 3 years of professional experience in embedded hardware or complex electronic-board design.
• Demonstrated experience designing complex mixed-signal boards with more than 12 PCB layers.
• Hands-on experience with boards containing high-speed digital interfaces, sensitive analog circuitry, RF signal paths, switching regulators, and low-noise linear regulators on the same PCB.
• Strong experience with high-speed hardware design involving interfaces such as: • JESD204B/C
• SERDES operating above 10 Gbps
• PCI Express
• DDR3 or DDR4
• High speed LVDS
• Gigabit or multi gigabit Ethernet
• USB
• Practical experience implementing JESD204B/C interfaces using high speed ADCs or DACs and FPGAs.
• Strong understanding of JESD204B concepts, including device and lane configuration, clocking, SYSREF, synchronization, deterministic latency, link initialization, and link debugging.
• Strong understanding of PCIe architecture and board-level implementation requirements, including differential routing, reference clocks, reset sequencing, impedance control, channel loss, connectors, and signal-integrity considerations.
• Strong understanding of signal integrity and power integrity for high-speed mixed-signal designs.
• Ability to define and review PCB layout constraints for: • Differential pair routing
• Controlled impedance traces
• Length and phase matching
• Via structures and stubs
• Reference-plane continuity
• Return current paths
• Crosstalk control
• Connector transitions
• Power distribution networks
• Clock and SYSREF distribution
• Analog, digital, RF, and power-domain isolation
• Experience reviewing PCB layouts and working closely with PCB layout engineers. Detailed hands on PCB layout experience is beneficial but is not mandatory.
• Working knowledge of RF design principles, including 50-ohm transmission lines, impedance matching, RF filtering, return loss, insertion loss, grounding, shielding, and component placement.
• Experience designing power architectures using buck converters, point of load regulators, and LDO regulators on the same board.
• Understanding of switching-regulator layout, power-loop minimization, compensation, sequencing, transient response, ripple, noise filtering, and thermal considerations.
• Experience with FPGA based circuit design, including power rails, configuration, clocking, high speed transceivers, memory interfaces, and I/O-bank planning.
• Experience using schematic capture and electronic design automation tools.
• Familiarity with signal integrity and power integrity simulation tools.
• In depth knowledge of EMI/EMC principles and mitigation techniques for mixed-signal, RF, and high-speed digital systems.
• Knowledge of PCB fabrication, assembly, stack up development, controlled impedance, high density interconnect processes, and manufacturing constraints.
• Experience with hardware bring up, laboratory debugging, and test equipment such as oscilloscopes, spectrum analyzers, vector network analyzers, logic analyzers, protocol analyzers, and power analyzers.

Preferred

• Knowledge of space grade and radiation tolerant components.
• Familiarity with relevant space and military standards, including MIL-STD-883 or equivalent standards.
• Experience with environmental qualification, vibration testing, thermal-vacuum testing, EMI/EMC testing, and reliability analysis.
• Experience with radiation-effects considerations, derating, component screening, failure-mode analysis, and worst-case circuit analysis.
• Familiarity with high-speed ADC and DAC clock-tree design, including low-jitter clock generation, clock distribution, synchronization, and phase-noise requirements.
• Experience with SI/PI simulations, including S-parameters, eye diagrams, channel analysis, crosstalk analysis, and power-distribution-network impedance analysis